module dut_8channel (
		//input
		async_rxd,   //signal from dut
		check_over,  //signal from dut
		clk_1m,		 //signal from dut
		clk_250k,
		oe_8ch,			 //signal from dut
		rst_n,		 //signal from dut
		sram_ack, //arbitrator  sram_ack signal
		sram_busy,//arbitrator sram_busy signal
		sram_data_out,// data from scram ctrl 
	
		//output
		jud_err,   //dut jud_err
		end_flag,   //dut end_flag
		sram_addr,  //arbitrator 
		sram_rd	,	//arbitrator
		rxd_fliter,
		oe_128,
        data,
        data_val
);
parameter N = 8;
input [N-1:0] async_rxd;
input check_over,
	  clk_1m,
	  clk_250k;
input [7:0] oe_8ch;
input rst_n,
	  sram_ack,
	  sram_busy;
input[7:0] sram_data_out;
	  
output [N-1:0] jud_err;
output [N-1:0] end_flag;
output [12:0] sram_addr;
output sram_rd; 
output [N-1:0]  rxd_fliter;
output [N-1:0]  oe_128;
output [N-1:0]  data,
                data_val;
	   
	  

wire	jud_err0,jud_err1,jud_err2,jud_err3,
		jud_err4,jud_err5,jud_err6,jud_err7;
		
wire	[N-1:0]	sram_data_out,
				ch_req,
				ch_ack;

wire [103:0] ch_addr;
wire [12:0]	addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7;			
wire  ack0,ack1,ack2,ack3,ack4,ack5,ack6,ack7,
	  req0,req1,req2,req3,req4,req5,req6,req7;
wire  manc0,manc1,manc2,manc3,manc4,manc5,manc6,manc7;

wire  	end_flag0,end_flag1,end_flag2,end_flag3,
		end_flag4,end_flag5,end_flag6,end_flag7;
wire    clk_250k;
wire    rxd_fliter7,rxd_fliter6,rxd_fliter5,rxd_fliter4,
        rxd_fliter3,rxd_fliter2,rxd_fliter1,rxd_fliter0; 
wire    oe_128_7,oe_128_6,oe_128_5,oe_128_4,
		oe_128_3,oe_128_2,oe_128_1,oe_128_0;
wire    oe_ch7,oe_ch6,oe_ch5,oe_ch4,
        oe_ch3,oe_ch2,oe_ch1,oe_ch0;
wire    data0,data1,data2,data3,data4,data5,data6,data7;
wire    data_val0,data_val1,data_val2,data_val3,
        data_val4,data_val5,data_val6,data_val7;
    
assign {ack7,ack6,ack5,ack4,ack3,ack2,ack1,ack0} = ch_ack;
assign ch_req  =  {req7,req6,req5,req4,req3,req2,req1,req0};
assign ch_addr =  {addr7,addr6,addr5,addr4,addr3,addr2,addr1,addr0};
assign  {manc7,manc6,manc5,manc4,manc3,manc2,manc1,manc0}  = async_rxd;
assign {oe_ch7,oe_ch6,oe_ch5,oe_ch4,oe_ch3,oe_ch2,oe_ch1,oe_ch0} = oe_8ch;
//assign  end_flag = 8'b11111111;
//assign  jud_err  = 8'b10100000;
assign end_flag   = {end_flag7,end_flag6,end_flag5,end_flag4,end_flag3,end_flag2,end_flag1,end_flag0};
assign jud_err    = {jud_err7,jud_err6,jud_err5,jud_err4,jud_err3,jud_err2,jud_err1,jud_err0};
assign rxd_fliter = {rxd_fliter7,rxd_fliter6,rxd_fliter5,rxd_fliter4,rxd_fliter3,rxd_fliter2,rxd_fliter1,rxd_fliter0};
assign oe_128     = {oe_128_7,oe_128_6,oe_128_5,oe_128_4,oe_128_3,oe_128_2,oe_128_1,oe_128_0};
assign data       = {data7,data6,data5,data4,data3,data2,data1,data0};
assign data_val   = {data_val7,data_val6,data_val5,data_val4,data_val3,data_val2,data_val1,data_val0};

arbitrator arb(//input
				.clk(clk_1m),
				.rst_n(rst_n),
				.ch_req(ch_req),
				.sram_ack(sram_ack),
				.ch_addr(ch_addr),
				.sram_busy(sram_busy),
				//output
				.sram_rd(sram_rd),
				.sram_addr(sram_addr),
				.ch_ack(ch_ack)
			);

code_jud dut0(
	//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.oe(oe_ch0),
		.check_over(check_over),
		.async_rxd(manc0),
		.sram_ack(ack0),
		.sram_data_out(sram_data_out),	
	//output
		.sram_addr(addr0),
		.sram_wr(),
		.sram_rd(req0),
		.end_flag(end_flag0),		  
		.jud_err(jud_err0),
		.rxd_fliter(rxd_fliter0),
		.oe_128(oe_128_0),
        .data(data0),
        .data_val(data_val0)
        
);
code_jud dut1(
	//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.oe(oe_ch1),
		.check_over(check_over),
		.async_rxd(manc1),
		.sram_ack(ack1),
		.sram_data_out(sram_data_out),	
	//output
		.sram_addr(addr1),
		.sram_wr(),
		.sram_rd(req1),
		.end_flag(end_flag1),		  
		.jud_err(jud_err1),
		.rxd_fliter(rxd_fliter1),
		.oe_128(oe_128_1),	
        .data(data1),
        .data_val(data_val1)
        
);
code_jud dut2(
	//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.oe(oe_ch2),
		.check_over(check_over),
		.async_rxd(manc2),
		.sram_ack(ack2),
		.sram_data_out(sram_data_out),	
	//output
		.sram_addr(addr2),
		.sram_wr(),
		.sram_rd(req2),
		.end_flag(end_flag2),		  
		.jud_err(jud_err2),
		.rxd_fliter(rxd_fliter2),
		.oe_128(oe_128_2),
        .data(data2),
        .data_val(data_val2)
);
code_jud dut3(
	//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.oe(oe_ch3),
		.check_over(check_over),
		.async_rxd(manc3),
		.sram_ack(ack3),
		.sram_data_out(sram_data_out),	
	//output
		.sram_addr(addr3),
		.sram_wr(),
		.sram_rd(req3),
		.end_flag(end_flag3),		  
		.jud_err(jud_err3),
		.rxd_fliter(rxd_fliter3),
		.oe_128(oe_128_3),
        .data(data3),
        .data_val(data_val3)
);
code_jud dut4(
	//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.oe(oe_ch4),
		.check_over(check_over),
		.async_rxd(manc4),
		.sram_ack(ack4),
		.sram_data_out(sram_data_out),	
	//output
		.sram_addr(addr4),
		.sram_wr(),
		.sram_rd(req4),
		.end_flag(end_flag4),		  
		.jud_err(jud_err4),
		.rxd_fliter(rxd_fliter4),
		.oe_128(oe_128_4),
        .data(data4),
        .data_val(data_val4)
);
code_jud dut5(
	//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.oe(oe_ch5),
		.check_over(check_over),
		.async_rxd(manc5),
		.sram_ack(ack5),
		.sram_data_out(sram_data_out),	
	//output
		.sram_addr(addr5),
		.sram_wr(),
		.sram_rd(req5),
		.end_flag(end_flag5),		  
		.jud_err(jud_err5),
		.rxd_fliter(rxd_fliter5),
		.oe_128(oe_128_5),
        .data(data5),
        .data_val(data_val5)
);
code_jud dut6(
	//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.oe(oe_ch6),
		.check_over(check_over),
		.async_rxd(manc6),
		.sram_ack(ack6),
		.sram_data_out(sram_data_out),	
	//output
		.sram_addr(addr6),
		.sram_wr(),
		.sram_rd(req6),
		.end_flag(end_flag6),		  
		.jud_err(jud_err6),
		.rxd_fliter(rxd_fliter6),
		.oe_128(oe_128_6),
        .data(data6),
        .data_val(data_val6)
);
code_jud dut7(
	//input
		.clk_1m(clk_1m),
		.clk_250k(clk_250k),
		.rst_n(rst_n),
		.oe(oe_ch7),
		.check_over(check_over),
		.async_rxd(manc7),
		.sram_ack(ack7),
		.sram_data_out(sram_data_out),	
	//output
		.sram_addr(addr7),
		.sram_wr(),
		.sram_rd(req7),
		.end_flag(end_flag7),		  
		.jud_err(jud_err7),
		.rxd_fliter(rxd_fliter7),
		.oe_128(oe_128_7),
        .data(data7),
        .data_val(data_val7)
);
endmodule




